This is an abridged version of 2026 RISC-V Market Report and Ecosystem Guide by the SHDgroup, provided at no charge thanks to the support of their sponsors. An unabridged version is also available with over 200 pages and comes with a spreadsheet containing over 300 tables of detailed information. In both versions, the intention is to provide a comprehensive examination of the rapidly expanding semiconductor market, including how it is evolving alongside the concurrent emergence of RISC-V and the influence of AI. The accelerating build-out of data centers for AI inferencing and training and Large Language Models (LLMs) is having a profound impact on semiconductor revenues worldwide. This impact extends to the adoption of the RISC-V ISA in an increasing number of SoCs aimed at including some level of AI functionality in the silicon solution. These impacts also extend to the Semiconductor Intellectual Property (SIP) vendors as they look to accommodate the acceleration of the different Neural Networks being used and EDA Tool vendors as they look to infuse AI functionality into their EDA tools to aid the productivity of silicon designers.

The introduction of RISC-V has fueled extensive CPU architectural exploration, visibly impacting device revenues, unit shipments, design starts, business models and IP licensing revenues on a global basis. The pervasive integration of AI across applications is a primary catalyst in today's semiconductor market. The RISC-V architecture has notably influenced SoC designers and architects and is poised to drive a substantial share of designs, revenues, and unit shipments in the coming years.

This month we received the new SpacemiT K3 board. Since its inception, felix86 wasn’t able to run on any of the out-of-order execution hardware, such as the SiFive P550 or the SOPHON SG2042. The former has no vector support, the latter has XTheadVector support. While initially there was consideration for supporting hardware without RVV 1.0 or hardware with XTheadVector, ultimately the decision was that we should instead focus on the future of RISC-V consumer hardware which will have RVV 1.0 due to it being mandatory in the RVA23 profile.

If you watched the felix86 talk at the RISC-V NA summit you might’ve seen a video of gameplay on K1 hardware. You would notice the lack of modern 3D games running on the emulator, because a lot of them would run at less than 5 frames per second. Now that we have much faster hardware, there’s more to show!

TLDW: Huge performance improvements over the K1, and RISC-V performance will only go up from here.

One of the RISC-V SoCs we have been most looking forward to this year is the SpacemiT K3 that features the X100 RISC-V cores that are RVA23 compliant and among the first readily available RVA23 RISC-V platform for running on the likes of Ubuntu 26.04 LTS. In this article is a preview of some very early benchmarks of the SpacemiT K3 with the new Pico-ITX single board computer offering.

The SpacemiT K3 features eight X100 RISC-V cores as well as eight ultra-wide parallel AI computing A100 cores. The X100 cores clock up to 2.4GHz and are RVA23 profile compliant and largely associated as delivering similar performance to the Arm Cortex-A76 cores. The A100 AI cores support INT4 / INT8 / FP8 / FP16 / BF16 and rated for around 60 TOPS API performance. The A100 cores are also among the few RISC-V cores so far available that support RVV 1.0 vector processing.

The SpacemiT K3 Pico-ITX is an interesting little board that pairs the K3 SoC with 10Gb networking, UFS storage, dual M.2 expansion slots, USB Type-C with power delivery and 4K DisplayPort output, and dual channel LPDDR5-6400 memory with 16GB and 32GB configurations offered.

BayLibre is proud to announce a successful collaboration with SpacemiT to enable initial functionalities of Android 16 on the SpacemiT K1 (RISC-V RVA22 + RVV 1.0) System-on-Chip (SOC). This achievement marks a significant step toward validating and accelerating Android enablement on high-end RISC-V platforms.

The main objective of this project was to validate the feasibility of porting modern Android to recent, high-performance RISC-V platforms. Furthermore, this work serves as crucial preparation for Android enablement on upcoming RISC-V profile RVA23 SOCs, as much of the effort and code will be directly reusable.

Built for Rapid Upstream Delivery

Rolling releases with upstream tracking bring new RISC-V features and fixes to you sooner—less waiting, less rework.

Built for RISC-V Developers

Stay close to upstream to reduce backports and forks. Easier reproduction, faster debugging, smoother upstream contributions.

Built for Early Validation

Surfaces firmware, platform semantics, and Linux interoperability issues early—so vendors fix faster, reduce divergence, and reach mainstream OS compatibility sooner.

This is formal specification of the RISC-V architecture, written in Sail.

The model specifies assembly language formats of the instructions, the corresponding encoders and decoders, and the instruction semantics. A reading guide to the model is provided in the doc/ subdirectory, along with a guide on how to add a new extension to the model.

The highlight of this release is substantially improved performance on Linux boot after a fix to the handling of superpages in the TLB.

This release adds 13 new extensions; all mandatory extensions for RVAU23 are now supported.

Several configuration parameters have been added, along with new command line options. The model implements a simple external interrupt generator, and the wait duration of instructions like WFI can be specified. The handling of misaligned accesses can bespecified at a more granular level.

RVA23 profile of RISC-V marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no longer optional accelerators bolted onto speculation-heavy cores. They are baseline capabilities that software can rely on.

RVA23 doesn’t force scalar execution to become deterministic. It simply makes determinism viable because the scalar side is no longer responsible for throughput. The vector unit handles the parallel work explicitly, and the scalar core becomes a coordinator that can be simple, predictable, and low‑power without sacrificing performance.

To understand why this shift matters, it helps to recall how thoroughly speculative execution came to dominate high-performance CPU design. It delivered speed, but at increasing cost—in power, complexity, verification burden, and security exposure. RVA23 does not reject speculation. Instead, it restores balance. It acknowledges that predictable, vector-driven parallelism is now a credible, mainstream path for performance growth.

SpacemiT Key Stone K3 series chips adopt RISC-V isomorphic fusion computing technology, integrating SpacemiT's self-developed 8 high-performance computing cores X100 and 8 ultra-wide parallel computing AI cores A100, providing 130 KDMIPS general computing power and 60TOPS general AI computing power, and can run 30 billion parameter large models smoothly.

K3 series chips are mainly used in AI computers, intelligent robots, personal intelligent computing servers, edge intelligent computing servers, large model inference machines and other fields.

SpacemiT K3 is an upcoming RVA23-compliant 64-bit RISC-V processor based on X100 cores clocked at up to 2.5 GHz. So far, we had limited information, but SpacemiT gave remote access to one SpacemiT K3-powered server to Sander, and he was kind enough to share some system information and early benchmarks.