this post was submitted on 26 Nov 2024
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One of the reasons why it's harder for x86 is because the instruction set is simply more complex. You either need a decoder to turn it into simpler instructions, or more hardware to handle the complex instructions, both of which increase the number of transitors, and therefore power draw until we create a room temp superconductor
Both RISC and CISC decode into micro-ops regardless. Read the article, it goes into detail, the diagrams make it pretty clear if you don't want to read the whole article. Modern processors have no notable differences between RISC or CISC designs anymore in the way you described. The only thing RISC and CISC differs in is essentially just the interface that assemblers assemble code into. Which is different across ISAs anyways.
Thanks for taking the time to correct me. I shouldn't rely on elementary knowledge from a BSc that discussed chips from 3 decades ago.