I'd say it's more an unfortunate consequence of confusing industry terminology. Sub-nanometer refers to the process, not the finished size of the chip. Smaller processes can fit more transistors in the same space.

The term "5 nm" does not indicate that any physical feature (such as gate length, metal pitch or gate pitch) of the transistors is five nanometers in size. Historically, the number used in the name of a technology node represented the gate length, but it started deviating from the actual length to smaller numbers (by Intel) around 2011.[3] According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, the 5 nm node is expected to have a gate length of 18 nm, a contacted gate pitch of 51 nm, and a tightest metal pitch of 30 nm.[4] In real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption compared to the previous 7 nm process.

— https://en.wikipedia.org/wiki/5_nm_process

I agree that there should be a better way to describe these things. Why not describe the actual size like we used to. Quite strange.