@bitcrafter@CombatWombatEsq calling ARM a RISC architecture was always a bit sketchy with glorious multi-register loads/stores (we give thanks to St Sophie), but this is completely CISC territory - and a very good use of silicon, in my humble opinion.
Better than the Jazelle extension going into a billion hard drives that *do not have any java code in the firmware*
@bitcrafter @CombatWombatEsq calling ARM a RISC architecture was always a bit sketchy with glorious multi-register loads/stores (we give thanks to St Sophie), but this is completely CISC territory - and a very good use of silicon, in my humble opinion.
Better than the Jazelle extension going into a billion hard drives that *do not have any java code in the firmware*