My baseline understanding is that "NPUs," as such, are vector accelerators with perhaps lower precision and definitely lower peak TDP. I say this because much of the incremental ML research I've skimmed over seems to be around getting away with lower precision, dropping down to FP8 or even FP4 from FP16 when they can get away with it.
I'm still confused as to why and how this is an acceptable tradeoff to firing up an iGPU with precise power/TDP stepping. Perhaps one of those situations where the power budget and latency to fire up the whole GPU block or burst it to max power ends up costing as much as the actual calculation. I think for purposes of this discussion, we also need a source that sheds light on the architectural differences between NPUs and GPU shader/execution units.
I think in this case, the equivalent of a compiler error for undefined behavior would be a swiftly forgotten wire story entitled "Trump promotes cryptocurrency project" published on a Friday afternoon. Just one more scam among the flood, and not one that can be offered for easy monthly payments with a banner ad in the margins of an RSBN broadcast.