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Linux was called 'obsolete' in 1992, and now it powers servers around the world
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this post was submitted on 14 Sep 2026
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A genuine Nostradamus, here.
Kinda wish he was right about risc tbh
I would argue he was, but it's taking far longer than I'd like
Depends if you count ARM too. I was always confused between RISC and RISC-V, and what ARM has anything to do. As I understand ARM is based on RISC, but its closed source. And RISC-V is based on RISC, but open source. Is that correct?
ARM is absolutely RISC. It stands for Acorn Risc Machines (or maybe it's "Advanced" now?), and was even then a very cool and promising idea, although it lagged behind in speed for a long time. Until the StrongArm came out, I think.
RISC isn't a specific architecture, but moreso a design philosophy.
So is ARM. Every ARM processor is basically uniq, and that makes it efficient. That's the point of it. RISC as a design philosophy doesn't take over the industry, its specific implementations. My question is not what RISC is, but if ARM is based on RISC and how close it is in their designs to RISC-V. As I understand the company behind ARM took the RISC philosophy and created a closed source system.
ARM is a well-defined instruction set architecture (ISA), that in order to implement, must comply with that instruction set and be compatible with other implementations from other vendors.
RISC is not any sepcific ISA at all, but is rather a more generic term for any ISA that has a small amount of instructions.
RISC-V, on the other hand, is a well-defined ISA whose implementations are intercompatible with each other. RISC-V is a very specific, royalty-free ISA that comes out of UC Berkeley that adopts the RISC philosophy.
But that's not true. ARM isn't well defined and a single standard, like x86 are. ARM devices are not compatible to each other necessarily. I just had the genius idea to lookup online, I should have done that instead wondering what it is. According to Wikipedia: https://en.wikipedia.org/wiki/ARM_architecture_family
So I was correct after all. Also ARM is around since 41 years.
Yes, ARM is RISC but it is also well-defined. ARMv9 is backwards compatible with ARMv8. ARMv8 and v9 are 64-bit while ARMv7 and before were 32-bit. Even ARMv9 is technically compatible with ARMv7 because of Aarch32 but that's optional. ARM's versioning is more numerous than x86-64 (which also has v2, v3, etc) but that doesn't mean it's not well defined.
Not really. Unlike x86, an ARM implementation doesn't have to be compatible to any of the existing CPUs. That's because of its nature being RISC it can be adapted and changed. There is no core ARM set that has to be implemented by every ARM CPU like x86 does, so that base compatibility is guaranteed. Just because a few CPUs in the family were compatible, doesn't make the entire architecture design well defined... it cannot be by nature being a RISC implementation.
ARM has multiple revisions that are incompatible with each other, such as ARMv7 being incompatible with AARCH64, but each ARMv7 implementation is compatible with other ARMv7 implementations, and each AARCH64 implementation is comaptible with other ARCH64 implementations, otherwise something like Android APKs or Linux binaries built for AARCH64 would only be able to be run on SoCs from a single company instead of being able to run on SoCs from Qualcomm, Samsung, Nvidia, and Mediatek just the same like they are.
Just because ARM does not maintain backwards compatability does not invalidate my point.
It does. ARM is basically a set of RISC processors that each of them are different. There is no single ARM well defined instruction set, because every ARM CPU is incompatible and an implementation of the RISC idea. You cannot say ARM is well defined. But you can say x86 is well defined.
I mean 80s computers had ARM CPUs, that has nothing todo with todays ARM anymore. This is not what I would call "well-defined".
If backwards compatibility bothers you, then replace it with "a series of well defined ISAs", which still does not define the RISC philosophy as a whole, which is the entire point I'm trying to make.
This is exactly what I'm saying, its not well defined architecture. You never know if the next ARM CPU will be compatible or not to any existing variants.
What do you mean? ARM is a RISC CPU. The entire philosophy of RISC is that anyone can implement this RISC system, and no guarantees are made to be compatible with any prior CPU. We have RISC CPUs since the beginning of 80s.
RISC literally just means reduced instruction set architecture. Any CPU that has a small amount of instructions (defined somewhat arbitrarilly) is considered to be a RISC CPU as opposed to a CISC (complex instruction set architecture) CPU. The idea behind RISC is to improve performance by reducing bloat, but the tradeoff is that performing more complex tasks takes more instructions to do.
Yes, but they could have compatibility like x86. The difference is that every CPU creator can have different sets, not just a superset. That's why ARM is not well defined, because its by nature cannot be. There is no definition of what an ARM or RISC CPU has to offer or be compatible to.
ARM is a series of ISAs, which are strict definitions which CPUs must conform to to be considered ARM compatible. RISC has no set or sets of ISAs, and is more of a philosophy.
If one company, like Mediatek or Qualcomm makes an AARCH64 CPU, compiles a binary for a common operating system, like Linux, and wants to run it on the others' CPU, that is possible because the ISA for AARCH64 is strictly defined.
On the other hand, take two incompatible RISC architectures, say one CPU that uses MIPS and another RISC-V, and try to run binaries compiled for the other architecture, then try to run it. It will not run because they are inherently incompatible, even though they are both a subset of the wider RISC umbrella.
Also depending on which ARM assembly programmer you ask, modern ARM isn't even really RISC due to its complexity despite the name. That is a whole other unrelated conversation, though.
Interesting read: https://www.dfrobot.com/blog-13483.html